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Pentek, Inc.

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Pentek Introduces High-Speed Software Radio PMC Module with Power Meter and Beamforming Capabilities

High-Density, Single-Slot Virtex-5 FPGA Software Radio Solution. Four 16-bit, 200 MHz A/Ds with 32 FPGA-based DDCs. Extended DDC Bandwidth Range from 20 kHz to 10 MHz.

Upper Saddle River, NJ, June 26, 2008 --( Pentek, Inc., with its proven track record as a pioneer in software radio innovation, today introduced its Model 7152, a quad 200 MHz, 16-bit A/D digitizer with a 32-channel digital down converter (DDC) configured in a PMC format. This high-speed module employs a high-performance, factory-installed core for users who want to purchase a product with the critical signal-processing functions already installed and operational. It is well suited for fulfilling the requirements of real-time software radio, beamforming, signal-intelligence and radar systems.

"The 7152 is a welcome addition to Pentek's FPGA (Field Programmable Gate Array) installed-core, software radio family of products," said Rodger Hosking, vice president of Pentek. "What's new in the 7152 is the addition of DDC gain and phase adjustments; signal summation; and power meters with threshold detectors. And the range of decimation has been extended so it is now programmable from 16 to 8192. In addition, the factory-installed IP core saves the user the task of FPGA programming. Another important feature of the 7152, retained from previous designs, is the front-panel synchronization bus that simplifies the integration of larger, multi-channel systems,” concluded Hosking.

Model 7152 Installed IP Core
Pentek has been extremely successful in implementing the high-performance, pre-installed DDC intellectual property (IP) cores for Xilinx FPGAs. By listening carefully to its customers, Pentek has equipped the Model 7152 with numerous functions essential to many communications and radar applications. Proprietary signal-processing techniques provide features such as 200 MHz sampling-rate DDCs, channel summation and power meters with threshold detectors.

Comparable solutions using ASICs or conventional FPGA structures would be much more expensive to implement. Multiple DDC chips and boards would be required to reproduce what is accomplished in one FPGA on a single module. Other existing DDC IP cores in the market not only use resources much less efficiently, but they also deliver limited performance.

Pricing and Availability
For the latest pricing and availability information, please contact Mario Schiavone by phone at (201) 818-5900 ext. 229, or by email to

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Contact Information
Pentek, Inc.
Mario Schiavone
To schedule an interview with Rodger Hosking, please contact Patterson & Associates.

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