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nSys Design Systems Pvt. Ltd.

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nSys Announces Functional Coverage Test Suites for Upcoming PCI Express® 3.0 Specification

Newark, CA, June 26, 2010 --( nSys Design Systems, offering the world’s largest portfolio of Verification IPs, announced the availability of Functional Coverage Test Suites for its nSys Verification Suite (nVS) for the PCI Express® (PCIe®)3.0 specification, currently under development within the PCI-SIG®.

The nSys Functional Coverage Test Suites use Coverage Driven Methodology that help engineers make sure that all possible significant combinations of variables, assertions & transitions have been covered in verification.

“A knowledgeable interpretation of PCIe specifications is important for design developers and the PCI-SIG values nSys’ contribution to the PCI Express architecture ecosystem through Verification IPs,” said Al Yanes, chairman and president of the PCI-SIG. “The PCI-SIG appreciates nSys’ participation at various PCI-SIG events - offering support as member, sponsor, speaker and exhibitor - as nSys helps to facilitate better understanding and adoption of the PCIe specification.”

"Our Test Suites for the upcoming PCIe 3.0 specification allow quick and extensive testing of the entire functionality of PCIe 3.0 designs," explains Jitendra Puri, Engineering Director, nSys. "Our Functional Coverage Test Suites help answer the crucial verification question- When to stop verifying for PCIe 3.0 designs?" he adds.

About nSys Functional Coverage Test Suites: Functional Coverage Test Suites are designed to ensure that 100% functional coverage is achieved for the design. These are available with an exhaustive set of coverage bins designed to verify completeness of Verification for different generations of PCIe designs.

About nSys: nSys offers the World’s Largest portfolio of Verification IPs for standard interfaces/ protocols such as PCIe 3.0/ 2.0/ 1.0, PCI-X, PCI, SR-IOV, Ethernet (100/ 40/ 10/ 1G), Interlaken, USB 3.0/2.0, SATA 3.0, SAS 3.0, ATAPI, AXI, APB, AHB, DDR3/2… Each nVS consists of BFM, Monitors, Assertion-based Checkers and Test Suites for Compliance Testing & Functional Coverage. All nVS are available in native SystemVerilog (OVM/ VMM) & Verilog, with option of Source Code. nVS family of VIPs is integrated to work with popular languages, like ‘e’, SystemC, OpenVera and VHDL, on all commonly used simulators and platforms. nSys also offers Verification Services like Independent Verification Services, SystemVerilog Migration and Verification Consulting. For more information, please visit

Contact Information
nSys Design Systems
Prachi Khaneja
1-888-679-7462 x 716

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