Fairport, NY, October 26, 2013 --(PR.com
)-- Saelig Company, Inc. has introduced TimingDesigner, an interactive timing analysis software application that delivers fast and accurate results for estimating timing design and signal integrity issues. It is ideal for high-speed, multi-frequency designs where it is essential to accurately model and analyze signal relationships between devices on a board or between embedded functions on an ASIC or programmable IC. TimingDesigner can evaluate comprehensive sets of timing alternatives and provide direction to the most complex of timing challenges, enabling designers to manage and monitor timing margins through the design process.
TimingDesigner is a complete analysis and documentation solution with built-in high accuracy analysis engines and an extensive online timing model library, with enhanced interfaces for board-level designers using Cadence OrCAD(R) Capture and Cadence Allegro(R) PCB design tools. Users can import EDIF files from OrCAD Capture to automate the creation of design components and ports for new projects within TimingDesigner, resulting in increased productivity. In addition, TimingDesigner offers a seamless way to import net propagation delay information from Allegro PCB design tools, allowing users to increase the accuracy of their post-route net delay analysis results and identify unexpected timing closure issues.
These features, combined with patented timing algorithms, makes TimingDesigner the most robust timing-critical design tool available. Many supporting features have been incorporated into TimingDesigner to make styling and image exporting easier. A WYSIWYG editor enables users to quickly create documentation from screen information, exported as a scalable image file, which is much quicker and easier than taking screen shots of the workspace. A print preview capability allows users to print directly from the tool. Additionally, users have multiple options and control mechanisms for defining fonts, colors, fills, line thicknesses, and more.
TimingDesigner can import pre-defined diagram styles as style groups which can be applied to the target diagram automatically or on an individual basis. This makes it very easy to adhere to defined corporate standards when generating timing diagrams for documentation. And with the multi-diagram interface, users can view and edit multiple diagrams and spreadsheets, much like opening multiple tabs in an internet browser. Information can be easily compared, copied, and pasted between tabs.
As products become more complex, so does the analysis required to accurately describe and validate a design. TimingDesigner projects can contain many diagrams describing different operations of the design, with each of these diagrams containing dozens of waveform options and potentially hundreds of associated timing parameters. Managing this much data can become a significant design challenge, especially when trying to meet tight delivery schedules. TimingDesigner helps engineers manage this mass of design data. User-definable parameter groups allow designers to group common timing factors together for quick and easy access. Additionally, a filtering tool can automatically hide parameters that do not match the significant criteria, making it easier to find the parameters sought for and hiding the parameters that are not of interest.
An introductory video can be viewed and an On-Demand Webinar is available online.
TimingDesigner provides a very powerful platform for timing analysis and optimization, with the ability to also generate customer-ready and timing-accurate documentation directly from the diagrams used for timing analysis.
A free 10-day trial of TimingDesigner 9.3 can be requested through Saelig’s shopping cart. For detailed specifications, free technical assistance, or additional information, please contact Saelig at 888-772-3544.